Changes between Version 1 and Version 2 of Component/Mips32


Ignore:
Timestamp:
Sep 8, 2008, 1:26:20 PM (17 years ago)
Author:
Nicolas Pouillon
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • Component/Mips32

    v1 v2  
    77It implements all instructions defined in the MIPS32 architecture specification, with the following limitations:
    88 * The floating point instructions are not supported
    9  * The virtual memory instructions are not supported, as an external TLB (SoCLib generic MMU) is implemented in the [wiki:Component/VciVcacheWrapper VciVcacheWrapper] component.
     9 * The Mips virtual memory instructions are not supported. The MMU is implemented as an external TLB (SoCLib generic MMU) in the [wiki:Component/VciVcacheWrapper VciVcacheWrapper] component.
    1010
    1111Both little-endian and big-endian implementations are available.
    … …  
    2929This component has no template parameters.
    3030
    31 == Constructor parameters ==
    32 
    33 == Visible registers ==
    34 
    35  The following internal registers define the processor internal state, and can be inspected:
    36  * r_pc : Program counter
    37  * m_ins : Instruction register
    38  * r_gpr[i] : General registers ( 0 < i < 32)
    39  * r_hi & r_lo : Intermediate registers for multiply / divide instructions
    40  * r_cp0[i] : Coprocessor 0 registers (0<=i<32). Implemented values:
    41   *  8: BAR : Bad address register
    42   * 12: SR : Status register
    43   * 13: CR : Cause register
    44   * 14: EPC : Exception PC register
    45   * 15: INFOS : CPU identification number on bits ![9:0]
    46 
    4731== Interrupts ==
    4832
    49 Mips defines 6 interrupts lines. ~~Le lowest number has the hiest priority.~~
     33Mips defines 6 interrupts lines.
    5034The handling and prioritization of the interrupts is deferred to software.
    5135