SoCLib components documentation

VCI Targets

• VciRam : A multi-segment embedded Ram controller
• VciMultiTty : A memory mapped multi-TTY controller
• VciMultiTimer : A memory mapped multi-Timer controller
• VciIcu : A memory mapped interrupt controller
• VciLocks : A memory mapped locks controller

VCI Initiators

• VciXcache : A generic data & instruction cache controller for 32 bits RISC processors
• VciDma : A DMA engine
• VciFdAccess : A component wrapping access to simulator file descriptors
• VciMwmrController : A component allowing access to Mwmr channels

VCI Interconnects

• VciVgmn : A VCI compliant generic micro-network
• VciLocalCrossbar : A VCI crossbar with a dedicated port to the global micro-network
• Pibus A VCI compliant PIBUS implementation.
• VciRing? : A VCI compliant ring interconnect.

• VciRingInitiatorWrapper : A VCI-Ring controler for a VCI initiator
• VciRingTargetWrapper : A VCI-Ring controler for a VCI target
• RingRegister? : A pipe-line stage for a Ring interconnect

• VciDspin : A VCI compliant DSPIN micro-network

• VciDspinInitiatorWrapper : A VCI-DSPIN protocol converter for a VCI initiator
• VciDspinTargetWrapper : A VCI-DSPIN protocol converter for a VCI target
• DspinRouter : The DSPIN router

Processor wrappers

• IssWrapper : A generic ISS wrapper, used to build CABA models for 32 bits RISC processors

Common utilities

• TtyWrapper : A simulator-side TTY abstraction tool, used by VciMultiTty
• MappingTable : A tool to declare and list all memory segments in a platform

Instruction Set Simulators

• Mips : Mips-R3000
• Ppc405 : PPC405
• MicroBlaze : MicroBlaze
• NiosII : NiosII