wiki:Component

Version 96 (modified by alain, 14 years ago) (diff)

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Processor ISS (Instruction Set Simulator)

These ISS must be wrapped in a CABA, TLM, or TLMDT wrapper to be used in a Soclib plat-form. Example of such a wrapper is the VciXcacheWrapper component.

Components

VCI Targets

  • VciRam : A multi-segment embedded Ram controller
  • VciSimpleRam : A multi-segment embedded Ram controller with parameterized latency
  • VciMultiTty : A memory mapped multi-TTY controller
  • VciXicu : A memory mapped Hardware interrupt + Timer + IPI controller
  • VciMultiTimer : A memory mapped multi-Timer controller
  • VciIcu : A memory mapped interrupt controller
  • VciLocks : A memory mapped locks controller
  • VciPCI : A bridge to the PCI bus
  • VciLogConsole : A memory-mapped text log sink
  • Mailbox : A mailbox component allows several processors to communicate via an interrupt mecanism

VCI Initiators

Iss Wrappers (caches)

Other initiators

VCI Interconnects

Dedicated coprocessors

Common utilities

  • MappingTable : A tool to declare and list all memory segments used in a platform and to define the memory mapping.
  • Loader : A binary-file loader (ELF, COFF, plain)
  • VciTargetFsm : A generic CABA submodule for handling the VCI fsm part of a target components, so that you can focus on the functionality
  • TtyWrapper : A simulator-side TTY abstraction tool, used by the VciMultiTty component
  • ProcessWrapper : A simulator-side fork/exec abstraction tool, with process' stdin/stdout communication
  • FbController : A simulator-side framebuffer abstraction tool